The desire for increasingly high performance of integrated circuits has driven integrated circuit designs to very high integration densities and extremely small device sizes. High integration density requiring minimization of the area occupied by each device not only increases the functionality that can be provided on a chip of a given size but reduced connection lengths between devices on an integrated circuit that reduces signal propagation time (increasing potential clock speed) and increases immunity to noise. However, scaling of traditional designs of devices such as field-effect transistors can compromise electrical characteristics such as control of the depletion layer in the transistor channel reducing the ratio of resistance in conductive and non-conductive states. The principal reason for compromise of depletion layer control is that reduced gate voltages necessary to reduce power dissipation requirements are unable to control the charge carrier population at increasing distance from the gate electrode and at corners of the conduction channel, even when the gate insulator is made very thin and when high dielectric constant (Hi-K) materials are used for the gate insulator.
To recover an adequate level of control of the depletion layer, so-called finFET transistor designs have been developed and increasing use of finFETs in integrated circuits is foreseeable. FinFETs are characterized by being formed with a thin, fin-shaped body of semiconductor material providing the source and drain regions with a conduction channel between them formed on an insulating surface allowing the transistor gate to be formed at least on opposing sides of the thin fin. The fin is often formed to have a width that is thinner than can be resolved lithographically to reduce the distance of any location in the fin from one of the gate electrode portions.
Several techniques of fabricating finFETs are known in the art, including so-called sidewall image transfer (SIT) which is capable of forming the fins with transverse dimensions smaller than can be resolved lithographically, sometimes referred to as sub-lithographic features. Sidewall image transfer involves forming a mandrel, forming sidewalls on the mandrel, removing the mandrel and removing portions of the remaining sidewalls that do not correspond to the desired fins and then using the remaining sidewall portions as a hard mask to form the fins. Therefore, SIT techniques are complex and include relatively critical processes with critical process tolerance windows and generally form many more fins in greater proximity than is desired in the completed integrated circuit.
A simpler fabrication technique, although requiring a comparable number of processes, is referred to as split-pitch lithography. Split-pitch lithography is based on the fact that, at feature sizes near the lithographic resolution limit and where features must be formed in close proximity to each other, the interference patterns caused by diffraction of lithographic exposure energy become critical since peaks in the intensity of the interference pattern can partially expose the resist (in which exposure is cumulative). Therefore, split-pitch lithography makes a resist exposure for patterning a hard mask using exposure masks with widely separated features and obtains proximity of features by replacing the resist and making another resist exposure using a different or offset mask after each respective pattern of widely spaced features is transferred to the hard mask; thus accumulating closely spaced features in the hard mask which is used to pattern the underlying layer(s) of material. As applied to fabrication of finFETs, however, split-pitch techniques also develop many more fins than needed and with closer proximity to each other than is desired which cause problems of fin removal and formation of isolation structures. Namely, removal of unwanted fin portions require additional masking to remove unwanted fins and fin portions regardless of the technique used to produce the fins.
This additional masking produces a structure in which the surface exposes the edges of thin, alternating regions of semiconductor (e.g. silicon) and a semiconductor oxide isolation regions (e.g. silicon oxide). Areas of this surface which are to be removed have a width several times that a fin and a relatively deep recess formed in underlying semiconductor material to form an isolation structure without excessively eroding a (preferably nitride) cap on the fin used for isolation structure etching.